Semiconductor arrangement

ABSTRACT

A semiconductor arrangement has an insulating protective layer composed of two sub-layers with a contacting window in the insulating layer, the outer sub-layer consisting, e.g. of Si3N4 in the contact window is conducted over the edge of the inner sub-layer consisting of SiO2, up to the semiconductor surface within the window, so that the SiO2 layer is screened from the contacting electrode and the alien ions (Na-ions) usually contained therein.

United States Patent [WI Wenzig et al.

[4 1 Sept. 9, 1975 SEMICONDUCTOR ARRANGEMENT [75] Inventors: WolfgangWenzig; Werner Spaeth,

both of Munich, Germany [73] Assignee: Siemens Aktiengesellschaft,Berlin Germany [22] Filed: Oct. 5, 1973 [21] Appl No; 403,916

Related US. Application Data Esch.... 29/578 Moyle 29/578 PrimaryExamlner--Wr Tupman Attorney, Agenr, 0r FirmHill, Gross, Simpson, VanSant en. Steadman, Chiara & Simpson [57] ABSTRACT A semiconductorarrangement has an insulating protective layer composed of twosub-layers with a con tacting window in the insulating layer, the outersublayer consisting, eg of Si INL in the contact window is conductedover the edge of the inner sub-layer consisting of SiO up to thesemiconductor surface within the window, so that the SiO layer isscreened from the contacting electrode and the alien ions (Na-ions)usually contained therein.

3 Claims, 3 Drawing Figures SEMICONDUCTOR ARRANGEMENT This is adivision, of application Ser. No. 287,709, filed Sept. 11, 1972 nowabandoned,

BACKGROUND OF THE INVENTION 1. Field of the Invention The presentinvention relates to semiconductor arrangements and more particularly tosemiconductor arrangements comprising a semiconductor crystal in whichat least one p-n junction meets a surface of the semiconductor crystalalong a closed curve, and an electrically insulating protective layercovering the p-n junction on the semiconductor surface, a window beingformed in the protective layer to accommodate an electrode contactingthe electrode surface within the closed curve along which the p-njunction meets the surface of the crystal.

2. Description of the Prior Art The semiconductor arrangements producedby the planar technique are usually, even during the production process,covered with an electrically insulating protective layer consisting ofsilicon dioxide. In addition, alumina AI O and silicon nitride Si N areem ployed as protective layer materials. Protective layers of this kindcan also, however, be applied as a protective coating of an alreadycompleted semiconductor arrangement, after the termination of the actualproduction process, even where a protective layer has already been usedas a diffusion mask and is still present.

SUMMARY OF THE INVENTION According to the present invention, there isprovided a semiconductor arrangement comprising a semiconductor crystalhaving a p-n junction the intersection of which with a surface of thecrystal follows a closed path, an electrically insulating protectivelayer covering the intersection of the p-n junction with the surface andconsisting of at least two sub-layers, an inner sublayer consisting ofsilicon dioxide in contact with the crystal surface, and an outersub-layer or layers consisting of an electrically insulating oxide of atrivalent metal of Group III of the Periodic System of the elementsand/or of beryllium oxide and/or of silicon nitride. A window is formedin said protective layer within the closed path formed by theintersection of the p-n junction with the surface, and an electrode incontact with the surface of the crystal within the window and spacedfrom the periphery thereof. The outer sub-layer or sub-layers extendingover the edge of the inner sub-layer at the periphery of the window andover and in contact with the surface of the crystal in the gap betweenthe periphery of the window and the periphery of the electrode.

In this way it is ensured that alien ions, in particular sodium ions,which would to a large extent diffuse through the SiO of the innersub-layer to the p-n junction, are prevented from penetrating into thissub-layer. The outer sub-layer is substantially impermeable to alienions of this kind, provided that it consists of one of theabove-mentioned materials. On the other hand, however, the p-n junctionis in direct contact with a part of the protective layer which isfavorable with respect to its electrical properties and which consistsof S As previously stated, the outer protective sub-layer or layers mayconsist of an oxide of a trivalent metal of the Group III of thePeriodic System, and/or of BeO and/or of Si N Layers of these materialsare electrically insulating and have adequate mechanical and dampresistance. Suitable oxides include Al O- S0 0 La. ,O and the oxides ofthe so-called ytterbia. However, because of the favorable influence ofits electric properties on the semiconductor surface at the p-njunction, the inner protective layer consists of SiO which may either beobtained pyrolytically from an appropriate reaction gas, or by thermaloxidation of the crystal surface when the semiconductor crystal consistsof silicon.

The presence of an outer sub-layer on the insulating protective layerappreciably improves the electrical stability and also the resistance toaging of the electrical properties of the semiconductor arrangement,provided that the outer sub-layer consists of one of the materialsmentioned above and is used in accordance with the invention.

In accordance with a further feature of the invention, the outer edge ofthe inner sublayer may also be covered by the outer sub-layer or layers,and this sub-layer or layers extend over a narrow zone of the surface ofthe crystal adjacent this outer edge.

By the use ofa composite protective layer on the surface of asemiconductor arrangement, according to the invention, the electricalproperties of the arrangement remain constant for a much longer timethan if only an SiO layer were used as the protective layer, or if theSiO protective layer was in fact covered with a second sub-layer, forexample, Si N but the edge of the SiO layer facing towards the electrodein the contacting window was not covered by this second sub-layerbecause the alien atoms, which mainly move over the SiO sub-layer andalong the peripheral area of this SiO sublayer, are prevented by theouter sub-layer, consisting of one of the above-mentioned materials,from penetrating into the SiO; sub-layer and from advancing to thecritical parts of the p-n junction. In order to achieve this, it issufficient if the outer sub-layer has a thickness of only 1000 A, andthe zone of the direct contact between the outer sub-layer and thesemiconductor surface has a width of the same order of magnitude. Theconstancy of the electrical properties which is obtained is at leasttimes better if the protective layer is provided in accordance with theinvention.

In order to produce a semiconductor arrangement in accordance with theinvention, after the production of the p-n junction and the SiOsub-layer of the insulating protective layer, and also of at least onewindow penetrating to the semiconductor surface in this inner sublayerwithin the closed path produced by the intersection of the p-n junctionat the surface, the entire surface of the arrangement is coated with theouter sublayer, and the material of the outer sub-layer is thereafterremoved again within at least one of the windows in the inner sub-layeronly to such an extent that in the center of the window thesemiconductor surface is ex posed, but the edge of the inner sub-layerstill remains completely covered by the outer sublayer. The outersub-layer extends over a narrow zone within the periphery of the window,and finally, an electrode which contacts the semiconductor surface isapplied to the semiconductor surface exposed within the window.

If it is possible to produce the inner sub-layer of the insulatingprotective layer, i.e. of the SiO sub-layer by thermal oxidation of thesemiconductor surface, this method is preferred. This is the case whenthe semiconductor crystal of the arrangement consists of silicon or ofsilicon carbide. Otherwise, it is possible to produce the SiO; sub-layerusing a known reaction gas. One possibility in this case consists in thethermal decomposition of a pure, gaseous, di-or trisiloxane, which iscaused to react on the heated semiconductor surface in the diluted state(the dilutent being, for example, argon). A further simple possibilityconsists in the oxidation of gaseous Sil-l, which, similarly dilutedwith argon, is applied to the heated surface of the semiconductorcrystal together with oxygen, for example in the form of air. This SiOsub-layer, if it is to be used as a diffusion mask, advantageously has athickness of 0.1 to 2 pm.

If the SiO, sub-layer is to be used as a diffusion mask, then, as isconventional in the planar technique, at least one window is etched intothis SiO layer in order to obtain a predetermined localization of thep-n junction or junctions. This etching is effected with the aid of aphotolacquer mask as an etching mask, which etching mask is produced inknown manner by the application of a photo-lacquer layer, its exposureat predetermined areas and its subsequent development. The developedlayer forms the etching mask and dilute hydrofluorix acid is used as anetching agent, which is caused to react on the parts of the SiO layerwhich are exposed at the windows in the photo-lacquer layer.

Even when the SiO sub-layer of the insulating protective layer is not tobe used as a diffusion mask, the Si must be locally etched away, againusing a photolacquer mask as an etching mask and dilute HF as an etchingagent, in order to expose the areas at which the semiconductor surfaceis to be contacted in a predetermined fashion. lf the SiO layer was usedas a diffusion mask, and if the doping substance which was diffused inwas used in the form of an oxide on a semiconductor crystal consistingof silicon, SiO newly formed at the diffusion windows must be removedagain in a predetermined manner. This can likewise be effected using aphoto-lacquer mask. in this case, however, if the whole of the newlyformed SiO is to be removed from the diffusion windows, a photo-lacquermask can be dispensed with; one merely makes use of the fact that theSiO: layer in the windows is considerably thinner than the SiO of themask, so that a brief overall etching with dilute aqueous HF solution,possibly buffered with NH, F, is sufficient to free the semiconductorsurface from SiO in the diffusion windows without substantially reducingthe thickness of the SiO layer elsewhere.

For the deposition of the second sub-layer, an appropriate knownreaction gas may similarly be caused to react at the surface of theheated crystal. The second sub-layer can, for example, have a thicknessof 1000 to 1500 A. As a reaction gas for the production of an A1 0layer, for example, trimethyl-aluminum, diluted with an inert gas may beused, which, in the presence of O is brought to act upon the surface ofthe crystal which is heated to 400 to 500C. Analogous compounds may beused for the reaction gas, if the outer sub-layer is to consist of Sc Oor Y O or 1.11 0 or another suitable oxide of the ytterbia series. Anouter protective layer of BeO may be obtained, for example, by thepyrolytic decomposition of beryllium formate (Be(- CHO which maylikewise previously be diluted with an inert gas. For the production ofa protective layer consisting of Si N a mixture of SiH NH; and Ar orlikewise hydrogen, can be allowed to react with the heated surface ofthe crystal at a temperature of between 800 and 900C.

The second sub-layer is deposited over the entire surface. ln order nowto produce a protective layer in accordance with the invention, theouter sub-layer must be locally removed again in such a manner that theinner sub-layer remains covered. For this purpose, a photo-lacquer maskis again required, the openings of which correspond to windows in theSiO;. sub-layer. They are, however, somewhat smaller and formed in suchmanner that when this photo-lacquer mask is used as etching mask, theSiO sub layer is nowhere exposed. As etching agents, either hotphosphoric acid or dilute hydrofluoric acid can be used. Thephotolacquer mask, when hot phosphoric acid is used, must be renderedresistant to this etching agent by a short period of heating to at leastC.

The application of the electrode or electrodes is effected in knownmanner, contact metal being applied to the crystal surface and alloyedor sintered-in at least at the contact areas of the semiconductorsurface which are exposed through the outer subsidiary layer. For this,a third mask is required either as a delimiting mask for the localizedapplication of the contact metal by vapor deposition orelectrodeposition, or as an etch ing mask for the predetermined removalof contact metal from areas where it is not required. If a plurality ofsemiconductor elements in accordance with the invention aresimultaneously to be produced in a single semiconductor wafer, obviouslyone requires as many diffusion masks as there are individual elements toinclude p-n junctions arranged one within another. On the other hand, itis desirable if the semiconductor surface is freed of every protectivelayer at the intended lines of division before division is carried out,particularly if the division is to take place by the engraving ofstraight scratch marks on the crystals surface and breaking along thesescratch marks. In this case, it is also advantageous if the doping ofthe semiconductor at the dividing points is not greater than that of theoriginal wafer, so that the lines of intended division are covered bythe diffusion mask during the diffusion process. (It has in fact beenfound that, for example, the engraving and breaking of the semiconductorwafer is rendered considerably more difficult by additional doping,particularly where silicon wafers doped with phosphorus are concernedinto which boron is additionally diffused in the lines of division).Finally the protective layer on all elements which are obtained by thedivision of the semiconductor wafer, should satisfy the requirements ofthe invention.

It is desirable that the need for an additional photolacquer mask forthis purpose, as was previously required for the production of the p-njunctions of the individual elements, should be avoided.

This may be achieved by making use of a process for the simultaneousproduction of a plurality of semiconductor elements, which are identicalwith one another, from a single semiconductor wafer, in which thediffusion mask which serves for the production of the or one of the p-njunctions, in particular the last p-n junction, of the individualsemiconductor elements, and which simultaneously forms the startinglayer for the production of the inner sub-layer of the insulatingprotective layer of each semiconductor element which is to be produced,is additionally provided with an auxiliary window which is spaced fromand surrounds the actual diffusion window as an annulus or frame, insuch manner that no p-n junction intersects that part of thesemiconductor surface which is exposed in the auxiliary window, and theinner edge of the auxiliary window encloses and is spaced from all thep-n junctions of the relevant semiconductor element, and that, moreover,no auxiliary window is connected to another of the auxiliary windows; inwhich one of the p-n junctions of the semiconductor elements is producedwith the aid of this diffusion mask; in which the contacting areas ofthe semiconductor surface and the semiconductor surface within theauxiliary windows are exposed and the outer sub-layer of the insulatingprotective layer is applied over the entire surface; in which the outersub-layer of the insulating protective layer is removed at thecontacting areas of the semiconductor surface and both sub-layers areremoved in the regions between adjacent auxiliary windows, in such amanner that the inner sublayer is nowhere exposed; in which the contactareas of the semiconductor surface are contacted; and in which, finally,the semiconductor wafer is divided into individual semiconductorelements at dividing lines extending exclusively between the regionsformerly occupied by adjacent auxiliary windows,

BRIEF DESCRIPTION OF THE DRAWING Other objects, featues and advantagesof the invention, its organization, construction and operation will bebest understood from the following detailed description of preferredembodiments thereof taken in conjunction with the accompanying drawingson which:

FIGS. 1 and 2 are similar schematic side sectional views, of part of asemiconductor wafer to illustrate two successive steps in themanufacture of a plurality of identical planar diodes according to theinvention; and

FIG. 3 is a plan view of the wafer part of FIG. 2.

DESCRlPTlON OF THE PREFERRED EMBODIMENTS In the drawing, two diodes Aand B only are shown. Over the entire wafer, however, the semiconductorcomponents will be arranged spaced apart from one another in rows andcolumns forming an orthogonal matrix, in such a manner that thesemiconductor components could be brought into register with one anotherby translation only ie without rotation), and that be tween adjacentrows and columns of this whole arrangement, there in each case remains asufficiently wide, rectilinear strip outside auxiliary windows which areassigned to the individual semiconductor components and whichindividually surround the latter at a distance to permit the division ofthe wafer by cutting or breaking without danger to the components.

Referring to the drawing, a semiconductor wafer 1 which consists, forexample, of n-conducting monocrystalline silicon, is first covered withan SiO layer 2 which forms the starting point for the production of adiffusion mask and for the inner sublayer of an insulating protectivelayer. Such a diffusion mask is required for the production of p-njunctions 8 and 9 belonging respectively to the individual diodes A andB. In order to produce this mask, a photo-lacquer etching mask isrequired. This etching mask is formed in known manner by means of theknown photoresist technique in such a way that, in addition to diffusionwindows 3 and 4 which serve for the production of the p-n junctions 8and 9, the SiO layer 2 is provided with ring-shaped or frame-shapedauxiliary windows 5 and 6, respectively, each of which surrounds arespective diffusion window and extends through the layer 2 to thesilicon surface. A strip 7 of the semiconductor surface be tween theauxiliary windows 5 and 6 remains covered by the layer 2.

The arrangement prepared in this way is heated, for example, in anoxidizing atmosphere containing B 0 vapor, to produce p -zones havingp-n junctions 8 and 9 in the basic material of the semiconductorcrystal. At the diffusion windows 3 and 4 there is thus respectivelyformed p-n junctions 8 and 9 each of which is in the form of a troughinlet into the silicon surface; these junctions form the p-n junctionsof the individual diodes A and 8. Because of the presence of theauxiliary windows 5 and 6, however, further p -zones are produced at thesame time, each of these zones surrounding and being spaced from one ofthe zones 8 and 9 of the diodes A and B, so that therefore eachindividual arrangement is provided with an additional p-n junction, 10or 11, which does not participate in the action of the component.

These additional p -zones can be used as protective rings. It is alsopossible to transfer other electrical functions to these zones and tothe p-n junctions 10, 11 which delimit them from the basic material ofthe crystal, particularly when these closed p-n junctions l0 and 11which resemble grooves surrounding the p-n junctions 8 and 9,respectively, are arranged at such a small distance from these p-njunctions that an electrical influence, for example, by minority chargecarrier injection, can take place. If these ti -zones are contacted, itmust be ensured that the electrodes nowhere contact the inner sub-layer2. Moreover, care must be taken that when the surface strips 7 areexposed between the auxiliary windows 5 and 6, the outer edge of the p-njunctions l0 and 11 is covered, at least by the outer sub-layer 12 ofthe insulating protective layer which is subsequently applied.

in general, however, the p-n junctions l0 and 11 which have been formedat the auxiliary windows 5 and 6 will not be used commercially, andprotective rings and other ring-shaped or frame-shaped p-n junctions, ifthey are to participate in the electrical function of the individualsemi-conductor components, will be arranged within the semiconductorregions surrounded by the p-n junctions l0 and 11.

The state of the arrangement which is represented in FIG. 1 occursimmediately after the diffusion process which leads to the formation ofthe p-n junctions 8, 9, l0 and 11 has been effected, and after theremoval of any films of silicon dioxide which may possibly have beennewly formed (and which contain a large amount of doping substance) onthe silicon surface in the windows 3, 4, 5 and 6. The surface of thearrangement is now coated with an outer sub-layer 12, which is thenremoved again at the areas 14 at which contacting of the zones 8 and 9is to be effected, within the former diffusion windows 3 and 4. Both ofthe sub-layers 2 and 12 forming the protective layer are removed at theregions 7 of the semiconductor surface. For this purpose, anappropriately designed further photo-lacquer etching mask is requiredwhich is formed in such a way that it covers the entire surface of thearrangement, with the exception of the intended contacting windows andthe regions 7 between the adjacent auxiliary windows and 6. Thecontacting windows are always made smaller than the diffusion windowswithin which they lie, so that in each case a strip 13, consisting ofmaterial of the sub-layer 12 remains around the contacting areas 14 onthe silicon surface.

If the outer sub-layer 12 consists, for example, of Si N deposited at800C, or at even higher temperatures, from the reaction gasesconventionally used for this purpose, hot phosphoric acid can, forexample, be used as the etching agent. Here too, a photo-lacquer maskproduced in the usual manner can be used as an etching mask after it hasbeen tempered for some length of time at above 100C. As a result of thetreatment, the silicon surface is exposed at the contact areas 14, andthe SiO sub-layer which covers the areas 7 is exposed. A subsequenttreatment with dilute HF also removes the SiO layer at the area 7 of thesemiconductor surface. If the outer sub-layer consists of one or more ofthe aforementioned metal oxides, etching with dilute HF can be used forthe production of the contact windows and the removal of both protectivelayers at the areas 7 between the auxiliary windows.

The exposed contact areas are also provided with electrodes in aconventional manner before the semiconductor wafer l is divided up intothe individual diodes A and B. This may be effected, for example, bymeans of a suitable mask, which is used either as a de' limiting maskfor localized application of the contact metal 15, or as a delimitingmask for the localized removal of contact metal applied in excess. Thedivision of the wafer 1 into the individual elements A and B is finallyeffected by engraving rectilinear lines 16 in the exposed strips 7between the former auxiliary windows 5 and 6 of the semiconductorsurface, and thereafter breaking up the wafer 1 into the individualelements A and B along the lines 16. In FIGS. 2 and 3 the state of thearrangement immediately before division is shown. Instead of completelyremoving the two sub-layers of the insulating protective layer at thepoint 7 as described above, it is also sufficient to free only a narrowstrip within the strip 7 from both insulating sub-layers, the lines 16then running in these narrow strips.

If more complex semiconductor elements then the semiconductor diodesrepresented in the drawing are to be produced, one of the diffusionmasks will also be provided with the additional frame-shaped orringshaped auxiliary windows, which annularly surround the actual zoneof the individual elements. In any case, it is advisable in this casealso, to provide the auxiliary windows in the diffusion mask whichserves for the production of the last pn junction of the individualelemerits.

in the contacting of the semiconductor zones lying between theindividual p-n junctions, corresponding contacting windows must alreadybe provided in the SiO sub-layer before the second sub-layer isdeposited.

Although we have described our invention by reference to specificillustrative examples. many changes and modifications of the inventionmay become apparent to those skilled in the art without departing fromthe spirit and scope of the invention. We therefore intend to includewithin the patent warranted hereon all such changes and modifications asmay reasonaly and properly be included within the scope of our contribution to the art.

We claim:

1. A process for the production of a plurality of identicalsemiconductor components in a single semiconductor wafer, comprising thesteps of: applying a layer of SiO on a surface of the wafer, the layerof SiO becoming a sub-layer of an insulating protective layer for eachindividual semiconductor component; forming a plurality of contactwindows in the SiO layer and a frame-shaped auxiliary window surroundingeach contact window; diffusing p-n junctions into the semiconductorwafer through the contact windows, the windows in the diffusion maskbeing dimensioned and spaced such that none of the p-n junctions opensinto the parts of the semiconductor surface which are exposed in theauxiliary windows; covering the Si0 sublayer including the side edgeswhich form said contact and auxiliary windows with a continuous outersublayer of an insulating protective layer consisting of an insulatingmaterial selected from the group consisting of Si N BeO, and an oxide ofa trivalent metal of Group [ll of the periodic system; removing theouter protective layer in areas of the contact windows to expose thesurface of the wafer while maintaining complete coverage of the SiOsub-layer; and forming a metal contact to the exposed wafer portion plusseparating the individual components from each other along lines ofdivision which extend exclusively within the areas between adjacentauxiliary windows.

2. The process according to claim 1 wherein the step of etching theauxiliary windows occurs prior to the diffusion step.

3. The method according to claim 1, wherein the step of separating theindividual semiconductor components from each other is further detailedby the steps of engraving lines in the semiconductor arrangement withinthe areas between adjacent auxiliary windows and breaking thearrangement along these lines.

1. A PROCESS FOR THE PRODUCTION OF A PLURALITY OF IDENTICAL SEMICONDUCTOR COMPONENTS IN A SINGLE SEMICONDUCTOR WAFER, COMPRISING THE STEPS OF: APPLYING A LAYER OF SI02 ON A SURFACE OF THE WAFER, THE LAYER OF SI02 BRCOMING A SUB-LAYER OF AN INSULATING PROTECTIVE LAYER FOR EACH INDIVIDUAL SEMICONDUCTOR COMPONENT, FORMING A PLURALITY OF CONTACT WINDOWS IN THE SI02 LAYER AND A FRAME-SHAPED AUXILIARY WINDOW SURROUNDING EACH CONTACT WINDOW, DIFFUSING P-N JUNCTIONS INTO THE SEMICONDUCTOR WAFER THROUGH THE CONTACT WINDOWS IN THE DIFFUSION MASK BEING DIMENSIONED AND SPACED SUCH THAT NONE OF THE P-N JUNCTIONS OPENS INTO THE PARTS OF THE SEMICONDUCTOR SURFACE WHICH ARE EXPOSED IN THE AXUALIARY WINDOWS, COVERING THE SI02 SUB-LAYER INCLUDING THE SIDE EDGES WHICH FORM SAID CONTACT AND AUXILIARY WINDOWS WITH A CONTINUOUS OUTER SUBLAYER OF AN INSULATING PROTECTIVE LAYER CONSISTING OF AN INSULATING MATERIAL SELECTED FROM THE GROUP CONSISTING OF SI3N4, BEO,
 2. The process according to claim 1 wherein the step of etching the auxiliary windows occurs prior to the diffusion step.
 3. The method according to claim 1, wherein the step of separating the individual semiconductor components from each other is further detailed by the steps of engraving lines in the semiconductor arrangement within the areas between adjacent auxiliary windows and breaking the arrangement along these lines. 